DLLs have been widely used for clock alignment in electronics systems. A VCDL is the key part of a DLL. In a DLL, variation of the loop gain can be caused by variation in VCDL gain, thus causing the loop bandwidth of the DLL to vary from the design target. The variations in the VCDL gain can result from VCDL nonlinear delay characteristics. Thus it is important that the VCDL has a linear delay characteristic over the full range of the control voltage. It is also desirable for a VCDL to have good duty cycle correction.
VCDLs are often implemented using current starved inverters. Different starving currents generate different delay times. However, the simple configuration of conventional current starved inverters results in very nonlinear delay characteristics. One method to solve this problem is disclosed in the reference to Christiansen (Jorgen Christiansen, “An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 7, July 1996). In the Christiansen reference, parallel connected input stages are added to the current starved inverters to get linear controllability. However, this method fails to achieve a linear delay characteristic over the full range of the control voltage.
Another method to reduce the effect of the variation of the VCDL gain on the DLL loop gain has been proposed by applying a self-biasing technique as disclosed in the reference to Maneatis (John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996). The current dependence of VCDL gain can be cancelled out, leading to loop bandwidth that tracks operating frequency. But this solution requires a complex DLL system design.
It would be desirable to have a VCDL with a linear delay characteristic over the full range of the control voltage. It would also desirable for the VCDL to have good duty cycle correction.